module ysyx_22040213_instfetch_port (
	  input rst,
	  // addr
	  input [63:0] pc, 
	  //req
//	  input pc_stall,   //for load to branch 
	  input IF_allow_in, //for pre-if ready go = 1 ,if allow_in = 0
	  //end req
	  output reg [63:0] if_inst,
	  output reg if_addr_ok,
	  output reg if_data_ok,

	  //sram port  
	  output o_if_wr,
	  output o_if_req,
	  output [2:0] o_if_size,
	  output [63:0] o_if_addr,
	  output [7:0] o_if_wstrb,
	  output [63:0] o_if_wdata,

	  input i_if_addr_ok,
	  input i_if_data_ok,
	  input [63:0] i_if_rdata
);
/*	//port//
	assign o_if_wr = 1'b0;
	assign o_if_req = pc_w_en && IF_allow_in;
	assign o_if_size = 3'b010;
	
	assign o_if_addr = pc;
	assign o_if_wstrb = 8'b00001111;
	assign o_if_wif = 64'b0;
	// end port//
	assign if_inst = i_if_rif;
	assign if_addr_ok = i_if_addr_ok;
	assign if_if_ok = i_if_data_ok;*/
	always @(*)begin
	  if(rst)begin
	    o_if_wr = 1'b0;
	    o_if_req = 1'b0;
	    o_if_size = 3'b0;
	    o_if_addr = 64'h0000000080000000;
	    o_if_wstrb = 8'b0;
	    o_if_wdata = 64'b0;
	    o_if_size  =3'b0;
	    o_if_wstrb = 8'b0;
	    if_addr_ok = 1'b0;
	    if_data_ok = 1'b0;
	    if_inst = 64'h0000000000000013;
	  end
	  else begin
	    o_if_wr = 1'b0;
//	    o_if_req = !pc_stall && IF_allow_in;
	    o_if_req = IF_allow_in;
	    o_if_wdata = 64'h0;
	    o_if_addr = pc;
	    o_if_size = 3'b010;
	    o_if_wstrb = 8'h0f;
	    if_inst = i_if_rdata;
	    if_addr_ok = i_if_addr_ok;
	    if_data_ok = i_if_data_ok;
	  end
	end

endmodule
